Senior EDA engineer — eight years designing power electronics, precision analogue circuits, and embedded systems from first-principle simulation to verified silicon.
Every topology verified in Ngspice or Qucs-S before a trace is routed. Failure modes are caught in software, not on the bench.
4–8 layer stackups with controlled impedance, thermal management, and DFM-clean Gerber output ready for JLCPCB and other CMs.
Every performance claim has a bench measurement behind it. Efficiency, ripple, and noise floor figures are instrument-verified.
Actively developing a GNN-based PCB routing advisor for KiCAD — applying machine learning to signal integrity constraints.
I am a senior EDA engineer with over eight years of hands-on experience spanning power electronics, analog circuit design, embedded systems, and RF subsystems. My work lives at the intersection of rigorous simulation and practical hardware reality.
My workflow is simulation-first: before a single trace is routed, I validate topology behaviour in Ngspice or Qucs-S, targeting known failure modes — loop instability, thermal runaway, ground bounce, and EMI susceptibility. The simulation model is a living document that must match bench measurement.
On the PCB side I work primarily in KiCAD for multi-layer layouts (4–8 layer stackups), applying controlled-impedance routing, split-plane strategies, and via stitching as deliberate engineering decisions. I have shipped hardware through full DFM/DFA review cycles to contract manufacturers including JLCPCB and know the gap between a clean schematic and a board that survives a production line.
My professional standard is simple: a design that hits specification first time, or carries a documented, traceable audit trail of every deviation, root cause, and correction.
Compact, manufacture-ready buck converter delivering up to 3 A with selectable output voltages (1.8 V / 3.3 V / 5 V / 12 V), full reverse polarity protection, and polyfuse crowbar — designed to JLCPCB basic parts constraints with day-one order capability.
jlcpcb/ folder| Parameter | Specification | Achieved |
|---|---|---|
| Input voltage range | 5.5 – 36 V | 5.5 – 36 V |
| Output current (continuous) | 3 A | 3 A (TPS5430 rated) |
| Selectable output voltages | 1.8 / 3.3 / 5 / 12 V | 4 options via solder bridge |
| Reverse polarity protection | Required | AO3401A P-MOS |
| Overcurrent protection | 3 A hold / 6 A trip | Polyfuse fitted |
| Fabrication readiness | JLCPCB direct order | Gerbers + BOM + CPL included |
Comprehensive, production-ready C++ driver for the TI ADS131M04 24-bit simultaneous-sampling delta-sigma ADC, optimised for the Raspberry Pi Pico platform with full datasheet feature coverage, interrupt support, and real-world noise mitigation.
convert() / revconvert() helpers for clean voltage-domain output| Feature | Status |
|---|---|
| Simultaneous 4-channel sampling | Implemented |
| Interrupt-driven DRDY support | Implemented |
| PGA / OSR / power mode control | Full register API |
| Offset & gain calibration | Implemented |
| Voltage conversion helpers | convert() / revconvert() |
| RP2040 SMPS noise guidance | Documented in README |
End-to-end system for capturing, analysing, and replaying 433 MHz OOK/ASK radio signals from commercial remote controls — combining hardware signal capture via HackRF, software demodulation via Universal Radio Hacker, and RP2040-driven faithful replay with enclosure.
.ook files for on/off/timer signals — parameterised signal playback with tunable timing and repeat counts| Parameter | Detail |
|---|---|
| Target frequency | 433.92 MHz ISM band |
| Modulation | OOK / ASK |
| Capture tool | HackRF One + URH |
| Transmitter | FS1000A module, XIAO RP2040 driven |
| Reverse-engineered devices | WEN 3410 / 3417 air filter remotes |
| Signal files | .ook on/off/timer captured & stored |
Multi-variant, open-hardware LoRa sensor node platform supporting both AVR128DB28 and STM32 MCUs with RFM95W LoRa radio — designed for long-range, battery-powered IoT deployments with modular optional components and full KiCAD files for immediate fabrication.
| Parameter | Specification |
|---|---|
| MCU variants | AVR128DB28 + STM32 |
| LoRa radio | RFM95W (Semtech SX1276) |
| LoRaWAN stacks | LMIC + RadioLib |
| Power options | LDO regulator, solar input, battery measurement |
| Fabrication | Aisler ready-to-order links |
| KiCAD files | Full schematic, PCB, PDF, custom libs |
Python tool that automates active and passive filter cascade design — computing component values from specification inputs and directly outputting production-ready KiCAD schematics, eliminating manual schematic entry for iterative filter development and Monte Carlo tolerance studies.
.kicad_sch files with correct net naming, component placement, and reference designators| Feature | Status |
|---|---|
| Active filter topologies (Sallen-Key, MFB) | Implemented |
| Passive filter synthesis (LC) | Implemented |
| KiCAD .kicad_sch export | Implemented |
| E-series component rounding | Implemented |
| Multi-stage cascade support | Implemented |
| Butterworth / Chebyshev / Bessel | Implemented |
pcbnew plugin generating automated SI audit reports: split-plane crossings, missing HF decoupling, unstitched ground regions, differential pair length mismatchespcbnew scripting under development to scale training dataI am currently open to senior and principal EDA engineering roles — full-time, contract, or consulting. If you need hardware that ships right first time, let's talk.